2019 先進扇出型與車用封裝技術研討會

  • 日期 :2019年 7月 2日
  • 地點 : 新竹

活動剪影

從2017年到2023年,整個半導體封裝市場的營收將以5.2%的複合年增長率(CAGR)增長,而先進封裝市場將以7%的複合年增長率增長,據市場研究機構Yole Development指出,此市場規模到2023年將增長至390億美元。另一方面,傳統封裝市場的複合年增長率則低於3.3%。在各種不同的先進封裝平台中,扇出型(Fan-out)封裝與車用高可靠度封裝 (Automotive Packaging),將分別以超過10%的複合年增長率快速增長。

目前國內外已有封裝廠、面板廠正積極佈局推動扇出型面板級封裝(Fan-out Panel Level Packaging),期望以成本與效能優勢製造更良好的收益。然而因面板級封裝製程尚未有共同標準,如面板尺寸、製程條件,因此如何掌握其相關技術進而達到低翹曲、高良率是其重大的挑戰。

車用電子更是下一個新興戰場。過去幾年仍在紙上談兵階段的先進駕駛輔助系統(Advanced Driver Assistance Systems;ADAS),今年2019 年已經在大部分的新世代國產車中,列為標準配備並且開始導入車聯網、AI 等各種技術,此一趨勢也將對 IC 封裝形式帶來改變。目前業界常見的可靠度問題是在溫度劇變的汽車應用環境下,其封裝體的molding compound內部產生脫層 (delamination) 導致晶片損壞,及封裝體與基板間的焊點非常容易產生翹曲變形,進而產生可靠度問題,而且此一狀況在高頻應用上會更加嚴峻,因為高頻系統的電路板必須選用特殊材質,不過此一材質在超過 Tg 的溫度時膨脹係數(CTE)會高達到 4 倍,翹曲問題會非常嚴重。

因應此趨勢,科盛科技將於7月2日於新竹台元科技園區舉辦「先進扇出型與車用封裝技術研討會」,聚焦目前Moldex3D針對此封裝技術發展的解決方案,邀請到來自清華大學、成功大學、日月光(ASE)、納美仕電子材料(Namics)及科盛科技的產業與技術專家從不同角度切入,深入討論先進扇出型與車用封裝技術的未來展望。

議程表

Time Topic
09:30-10:00 Registration
10:00-10:05 Opening
張榮語 執行長 | 科盛科技
10:05-11:05 Design of Panel/Wafer Level Fan-out Packaging Using Simulation with AI Based Technology
江國寧 講座教授 | 清華大學動力機械系
11:05-12:00 The Latest Moldex3D IC Package Solution on Advanced Package
徐志忠 部門協理 | 科盛科技
12:00-13:00 Lunch
13:00-13:50 CAE Simulation for IC Package : From Molding Analysis to Warpage Prediction
黃聖杰 教授 | 成功大學機械工程學系
13:50-14:40 Automotive Packaging, Technologies and Market Trends
李嘉炎 協理 | 科盛科技
14:40-15:10 Coffee Break
15:10-15:40 Characterization Analysis of Fan-out Package Technology Development
施孟鎧 部經理 | 日月光集團研發中心
15:40-16:10 Namics Underfill Roadmap in 2019
楊琮富 業務經理 | 台灣納美仕電子材料
16:10-16:40 Panel Discussion

※ 以上活動議程公司保有異動權利。

講師介紹

Design of Panel/Wafer Level Fan-out Packaging Using Simulation with AI Based Technology

江國寧
清華大學動力機械系 講座教授

Professor K. N. Chiang received his Ph.D. degree from the Georgia Institute of Technology, USA. Currently, he is the Chair Professor and Director of the Advanced Packaging Research Center of the National Tsing Hua University in Hsinchu, Taiwan. From 2010 to 2013, he served as Director of the National High-Performance Computing Center, which is the National Strategic Research Center of Taiwan. He has received three outstanding research awards from the Ministry of Science and Technology of Taiwan and has published more than 300 technical papers in SCI journals and conference proceedings. He has awarded more than 40 invention patents. Currently, he is Editor-in-Chief of the Journal of Mechanics (SCI), Senior Area Editor of the IEEE Transactions on Component, Packaging and Manufacturing Technology (SCI), and he was the Associate Editor of the 4 SCI Journal and the board member of IEEE-EPS.

He has made great achievements in simulation-based science and technology. He successfully combined simulation design with artificial intelligence technology and applied it effectively to semiconductor-related designs. His technology has greatly reduced product development time and development costs. Currently, Professor Chiang is the Chairman of Society of Theoretical and Applied Mechanics, Taiwan. He is the IEEE / ASME / STAM Fellow and the Academician of International Academy of Engineering (IAE), Russia.

The Latest Moldex3D IC Package Solution on Advanced Package

徐志忠
科盛科技 部門協理

Jim畢業於國立清華大學化學工程博士,他目前負責科盛科技產品處求解器開發部門的研發。在過去幾年中,Jim與客戶密切合作,合作過知名廠商,如矽品、日月光、聯測等,為客戶提供技術解決方案,以滿足產品開發時的需求。專業領域為開發數值模型,模擬實際成型過程,如IC封裝模擬、複合材料成型模擬,多相流成型模擬和,計算流體動力學,黏彈性應力鬆弛和結構變形的多物理行為。與團隊共同開發項目,構建數值模型和用戶工作流程,以提供高效能準確的軟體。他在射出成型,流體輔助射出成型和IC封裝等高分子加工領域擁有多項技術論文和產品專利。

CAE Simulation for IC Package : From Molding Analysis to Warpage Prediction

黃聖杰
成功大學機械工程學系 教授

黃聖杰教授1992年從美國伊利諾大學獲得博士學位後即回台灣成功大學機械系任教,其所從事之研究領域為IC封裝、塑膠加工、3D列印的製程模擬、機台發展與新技術開發。他在IC封裝領域的研究已有近30年經驗,主要是發展塑膠封裝模擬分析技術,由塑膠封裝模流分析著手,發展IC封裝體熟化後的翹曲變形預測及後熟化製程模擬,他所發展出來的P-V-T-C翹曲變形預測方法及後熟化分析方法目前已被證明有效且廣泛應用於業界。

Automotive Packaging, Technologies and Market Trends

李嘉炎
科盛科技 協理

Chia-Yen Lee received a Ph.D. in Power Mechanical Engineering from National Tsing Hua University, and started working in electronic packaging and assembly industrial over 10 years. During more than 10 years working experience, he has very deep and wide exposure from TSMC (foundry) as a technical manager for 3DIC packaging simulation, Delta Electronics (system) as a technical manager for power packaging design to Infineon Singapore (IDM) as a manager for packaging roadmap development. Until now, He held a total of 13 U.S. patents and published 3 SCI journal papers and 11 technical conference papers on electronic packaging field.

Characterization Analysis of Fan-out Package Technology Development

施孟鎧
日月光集團研發中心 部經理

Meng-kai Shih is a department manager with Product Characterization of Corporate R&D Center and currently leading the Stress-Thermal Analysis Lab development of System in Package, Panel Fan out technology , 2.5DIC product development, including package-level stress, thermal dissipation analysis and board-level structure reliability prediction at Advanced Semiconductor Engineering Inc. (ASE Group). He received the Ph.D. degree in Mechanical Engineer from the National Chung Cheng University, Chia-Yi, ROC, in 2006.

Dr. Shih has over 10 years of research focusing on finite element simulation and analysis electronic packaging manufacturing process, micro-force testing methods and IC failure mode analysis. Besides, he has over 30 technical publications of SCI journal and international conference papers. , and also is the inventor of more than 10 patents in US, China and Taiwan.

 

Namics Underfill Roadmap in 2019

楊琮富
台灣納美仕電子材料 業務經理

曾任職於工研院電光所電子構裝組製程工程師,台積電IIPD TSV module assembly技術副理。在2007年至2013年間,發表數篇半導體封裝領域相關之論文於ECTC, ICEP等研討會及Soldering & Surface Mount Technology, IEEE Transactions on Components, Packaging and Manufacturing Technology等期刊論文。在2011年,獲ICEP研討會,Outstanding Technical Paper Award。目前任職於台灣納美仕電子材料,擔任業務經理。

交通資訊

地址:新竹縣竹北市台元一街3號三期會館2樓 多功能會議室 (台元科技園區)

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Anita Chen
anitachen@moldex3d.com
03-5600199 ext. 703

 


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